1. Field of the Invention
This invention relates to a technique for programming a semiconductor memory device, and, in particular, to a programming system and method of an erasable programmable read only memory (EPROM).
2. Description of the Prior Art
A typical prior art EPROM structured around a single bit line is shown in FIG. 6. As is well known in the art, a plurality of memory cell transistors, such as FAMOSs or stacked-gate MOSs, M1, M2, . . . , have their drains connected to a bit line B, which is connectable to a programming high voltage V.sub.pp through a switching N-channel MOS transistor Q1. For example, upon completion of programming of the memory cell transistor M1, when the memory cell transistor M1 is set in a deselected state and another memory cell transistor M2 is set in a selected state, if the charge applied in the previous programming step still remains in the parasitic capacitance of the bit line B, the memory cell transistor M2 will be programmed unconditionally. In order to avoid this situation, a discharging N-channel MOS transistor Q2 is provided as connected to the bit line B so as to remove the charge prior to each programming step.
The on/off operation of the discharging transistor Q2 is controlled by a control signal N6. This control signal N6 is supplied through a buffer circuit C3 as an output signal of a two-input NOR gate N, which has one of its two input terminals connected to receive a signal SVP of the same polarity as that of a control signal N2 to be applied to the gate of the switching transistor Q1 and its other input terminal connected to receive a signal output from a timing generating circuit C1 when the signal SVP is applied to a signal level converting circuit C2 which is connected to the timing generating circuit C1. The signal SVP is converted to the programming voltage V.sub.pp by the signal level converting circuit C2. The timing generating circuit C1 is basically comprised of a one-shot circuit.
With reference to a timing chart shown in FIG. 7, the operation of programming the above-described prior art EPROM will be described. When the control signal N2 applied to the gate of the switching transistor Q1 and a selection signal N41 applied to the gate of the memory cell transistor M1 are set at the programming voltage V.sub.pp, programming is effected to the memory cell transistor M1. During this programming period, if the signal SVP becomes a high level or V.sub.cc level, the signal level converting circuit C2 supplies a V.sub.pp level output signal which is then supplied to the timing generating circuit C1, in which its N-channel MOS transistor Q3 is turned on and its N-channel MOS transistor Q4 is turned off so that a capacitor C comprised of a MOS transistor is charged through the transistor Q3. Since either of the two input signals to the NOR gate N is at high level until the programming is completed, the voltage at the gate of the discharging transistor Q2 remains at low level (ground GND level in the illustrated example) so that the transistor Q2 is maintained off.
Then, when the signal N2 changes from V.sub.pp level to low level and the signal N41 changes from V.sub.pp level to high level to complete the programming operation and at the same time when the signal SVP changes from high level to low level, both of the two input signals to the NOR gate N become low level to cause the signal N6 to become high level, so that the transistor Q2 is turned on, thereby discharging the charge stored in the parasitic capacitance of the bit line B (cf. N3 in FIG. 7). Then, at the timing generating circuit C1, the transistor Q3 is turned off and the transistor Q4 is turned on, so that the charge stored in the capacitor C is discharged through the transistor Q4. During this discharging process, when the voltage of the capacitor C becomes lower than the threshold voltage of an inverter I1 after a predetermined time period, one of the input signals to the NOR gate N becomes high level so that the signal N6 to be applied to the gate of the discharging transistor Q2 again becomes low level. This completes the programming operation of the single memory cell transistor M1.
However, in accordance with such a prior art programming method, it is required to provide not only the discharging transistor Q2 for each bit line B, but also a buffer circuit for driving the gate of the discharging transistor Q2. As a result, these elements make it harder to make an EPROM smaller in size or higher in density.